The present disclosure relates generally an integrated circuit (IC) device and, more particularly, to method for forming a gate structure.
As technology nodes shrink, in some IC designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution. One process of forming a metal gate stack is termed “gate last” process in which the final gate stack is fabricated “last” which allows for a reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in larger technology nodes.
There are challenges to implement such features and processes in CMOS fabrication. As technology nodes continue to decrease, particularly to the 22 nm technology node and beyond, the spacing between gate stacks continues to decrease, which affects the pocket/LDD implantation process. The issue becomes worse with a thick hard mask applied on a gate stack to increase the total thickness of the gate stack. A conventional hard mask layer needs to be thick as deposited due to its characteristics of being easily etched away in subsequent wet etch processes. If the hard mask layer is not thick as deposited, the remaining thickness of the hard mask layer after a wet etch process may not be sufficient for protecting the underlying material layer. However, the thick hard mask layer exacerbates the shadowing effects during pocket/LDD implantation process.